NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 351

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
Table 14-6 describes QIR fields.
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as
48 separate locations that comprise 16 words of transmit data, 16 words of receive data and
16 bytes of commands.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR].
This also causes the value in QAR to increment.
Correspondingly, a read at QDR returns the data in the RAM at the address specified by
QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait
state.
BIts
7–4
15
14
13
12
11
10
9
8
3
2
1
0
WCEFB Write collision access error enable. A write collision occurs during a data transfer when
WCEFE Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the
ABRTB
ABRTE
ABRTL
WCEF
SPIFE
Name
ABRT
SPIF
—
—
—
—
Chapter 14. Queued Serial Peripheral Interface (QSPI) Module
the RAM entry containing the command currently being executed is written to by the CPU
with the QDR. When this bit is asserted, the write access to QDR results in an access
error.
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a
transfer. When set, an attempt to clear QDLYR[SPE] during a transfer results in an
access error.
Reserved, should be cleared.
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR.
QDLYR[SPE] is only cleared by the QSPI when a transfer completes.
interrupt, and clearing it disables the interrupt.
Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the
interrupt, and clearing it disables the interrupt.
Reserved, should be cleared.
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the
interrupt, and clearing it disables the interrupt.
Reserved, should be cleared.
Write collision error flag. Indicates that an attempt has been made to write to the RAM
entry that is currently being executed. Writing a 1 to this bit clears it and writing 0 has no
effect.
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the
QDLYR rather than by completion of the command queue by the QSPI. Writing a 1 to this
bit clears it and writing 0 has no effect.
Reserved, should be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the
queue. Set on completion of the command pointed to by QWR[ENDQP], and on
completion of the current command after assertion of QWR[HALT]. In wraparound mode,
this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing
a 1 to this bit clears it and writing 0 has no effect.
Table 14-6. QIR Field Descriptions
Description
Programming Model
14-13