D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 167

MCU 3V 0K 100-TQFP

D12312SVTE25

Manufacturer Part Number
D12312SVTE25
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12312SVTE25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTE25
HD6412312SVTE25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.4.5
The chip is capable of fast word transfer instruction to on-chip memory, and the program area is
provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.9 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.9 are explained in table 5.10.
Table 5.9
No.
1
2
3
4
5
6
Total (using on-chip memory)
Notes: 1. Two states in case of internal interrupt.
Table 5.10 Number of States in Interrupt Handling Routine Execution
Symbol
Instruction fetch
Branch address read
Stack manipulation
Legend:
m: Number of wait states in an external device access.
Item
Interrupt priority determination *
Number of wait states until executing
instruction ends *
PC, CCR, EXR stack save
Vector fetch
Instruction fetch *
Internal processing *
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Interrupt Response Times
Interrupt Response Times
2
3
4
S
S
S
I
J
K
Internal
Memory
1
1
8-Bit Bus
2-State
Access
4
INTM1 = 0
3
1 to (19+2·S
2·S
2·S
2·S
2
12 to 32
K
I
I
Rev.7.00 Feb. 14, 2007 page 133 of 1108
Object of Access
3-State
Access
6+2m
I
)
External Device
Advanced Mode
Section 5 Interrupt Controller
2-State
Access
2
16-Bit Bus
INTM1 = 1
3
1 to (19+2·S
3·S
2·S
2·S
2
13 to 33
K
I
I
REJ09B0089-0700
3-State
Access
3+m
I
)

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