D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 821

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

17.29.3 Procedure Program and Storable Area for Programming Data
In the descriptions in the previous section, the programming/erasing procedure programs and
storable areas for program data are assumed to be in the on-chip RAM. However, the program
and the data can be stored in and executed from other areas, such as part of flash memory which is
not to be programmed or erased, or somewhere in the external address space.
Conditions that Apply to Programming/Erasing
(1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in
(2) The on-chip programming/erasing program will use the 128 bytes as a stack. So, make sure
(3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
(4) The flash memory is accessible until the start of programming or erasing, that is, until the
(5) The flash memory is not accessible during programming/erasing operations, therefore, the
(6) After programming/erasing, the flash memory should be inhibited until FKEY is cleared.
on-chip RAM, therefore, this area is not available for use.
that this area is secured.
executed in on-chip RAM.
result of downloading has been judged. When in a mode in which the external address space is
not accessible, such as single-chip mode, the required procedure programs should be
transferred to the on-chip RAM before programming/erasing of the flash memory starts.
operation program is downloaded to the on-chip RAM to be executed. The programs such as
that which activate the operation program, should thus be stored in on-chip memory other than
flash memory or the external address space.
The reset state (RES = 0) must be in place for more than 100 μs when the LSI mode is changed
to reset on completion of a programming/erasing operation.
RES
V
CC
Figure 17.95 Oscillation Stabilization Time, PROM Mode Setup Time, and
t
osc1
t
bmv
Memory read mode
Command wait state
Power-Down Sequence
Command acceptance
Auto-program mode
Auto-erase mode
Rev.7.00 Feb. 14, 2007 page 787 of 1108
Command wait state
Normal/abnormal
end identification
REJ09B0089-0700
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Section 17 ROM
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