D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 190

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

Section 6 Bus Controller
6.3.5
The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low
when the corresponding external space area is accessed.
Figure 6.3 shows an example of CSn (n = 0 to 7) output timing.
Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR),
CS167 Enable (CS167E), CS25 Enable, CSS17, CSS36, PF1CS5S, PF0CS4S for the port
corresponding to the particular CSn pin.
In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset.
Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding
control registers should be set when outputting signals CS1 to CS7.
In the ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a
power-on reset, and so the corresponding control registers should be set when outputting signals
CS0 to CS7.
For details, see section 8, I/O Ports.
Rev.7.00 Feb. 14, 2007 page 156 of 1108
REJ09B0089-0700
Chip Select Signals
Address bus
φ
CSn
Figure 6.3 CSn Signal Output Timing (n = 0 to 7)
T
1
Area n external address
Bus cycle
T
2
T
3