D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 290

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

Section 8 I/O Ports
Port A MOS Pull-Up Control Register (PAPCR)
Bit
Initial value : Undefined Undefined Undefined Undefined
R/W
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
Bits 3 to 0 are valid in modes 6 and 7 * , and all the bits are invalid in modes 4 and 5. When
PADDR bits are cleared to 0 (input port setting), setting the corresponding PAPCR bits to 1 turns
on the MOS input pull-up for the corresponding pins.
PAPCR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Port A Open Drain Control Register (PAODR)
Bit
Initial value : Undefined Undefined Undefined Undefined
R/W
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA3 to PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
All bits are valid in mode 7. *
Setting PAODR bits to 1 makes the corresponding port A pins NMOS open-drain outputs, while
clearing the bits to 0 makes the pins CMOS outputs.
PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 256 of 1108
REJ09B0089-0700
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:
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—
—
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7
7
—
—
—
—
6
6
—
—
—
—
5
5
—
—
—
—
4
4
PA3ODR PA2ODR PA1ODR PA0ODR
PA3PCR PA2PCR PA1PCR PA0PCR
R/W
R/W
0
0
3
3
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0