D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 425

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

10.1
The chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has
an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are
constantly compared with the TCNT value to detect compare match events. The 8-bit timer
module can thus be used for a variety of functions, including pulse output with an arbitrary duty
cycle.
10.1.1
The features of the 8-bit timer module are listed below.
• Selection of four clock sources
• Selection of three ways to clear the counters
• Timer output control by a combination of two compare match signals
• Provision for cascading of two channels
• Three independent interrupts
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input (enabling use as an external event counter)
The counters can be cleared on compare match A or B, or by an external reset signal
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output
⎯ Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1
⎯ Channel 1 can be used to count channel 0 compare matches (compare match count mode)
Compare match A and B and overflow interrupts can be requested independently
Channel 0 compare match A signal can be used as an A/D converter conversion start trigger
As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting
module stop mode
for the lower 8 bits (16-bit count mode)
Overview
Features
Section 10 8-Bit Timers
Rev.7.00 Feb. 14, 2007 page 391 of 1108
Section 10 8-Bit Timers
REJ09B0089-0700