D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 226

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

Section 7 Data Transfer Controller
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE
0
1
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-
shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
7.2.9
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP14 bit in MSTPCR is set to 1, DTC operation stops at the end of the bus cycle and
a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while
the DTC is operating. For details, see section 19.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev.7.00 Feb. 14, 2007 page 192 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
Module Stop Control Register (MSTPCR)
Description
DTC software activation is disabled
[Clearing conditions]
•
•
DTC software activation is enabled
[Holding conditions]
•
•
•
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
:
When the DISEL bit is 0 and the specified number of transfers have not ended
When 0 is written after a software activation data-transfer-complete interrupt is
issued to the CPU
When the DISEL bit is 1 and data transfer has ended
When the specified number of transfers have ended
During data transfer due to software activation
15
0
14
0
13
1
MSTPCRH
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
MSTPCRL
4
1
3
1
2
1
(Initial value)
1
1
0
1