D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 215

MCU 3V 0K 100-TQFP

D12312SVTE25

Manufacturer Part Number
D12312SVTE25
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12312SVTE25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTE25
HD6412312SVTE25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.8.3
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
• If the CPU is in sleep mode, it transfers the bus immediately.
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
6.8.4
External bus release can be performed on completion of an external bus cycle. The RD signal
remains low until the end of the external bus cycle. Therefore, when external bus release is
performed, the RD signal may change from the low level to the high-impedance state.
6.9
In a reset, the chip, including the bus controller, enters the reset state at that point, and any
executing bus cycle is discontinued.
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations. See appendix A.5, Bus States during Instruction Execution, for timings at
which the bus is not transferred.
Bus Transfer Timing
External Bus Release Usage Note
Resets and the Bus Controller
Rev.7.00 Feb. 14, 2007 page 181 of 1108
Section 6 Bus Controller
REJ09B0089-0700

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