D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 997

MCU 3V 0K 100-TQFP

D12312SVTE25

Manufacturer Part Number
D12312SVTE25
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12312SVTE25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTE25
HD6412312SVTE25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
TIOR3H—Timer I/O Control Register 3H
Initial value
Read/Write
Bit
:
:
:
Note: *
TGR3B I/O Control
0
1
IOB3
R/W
7
0
0
1
0
1
When bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as
the TCNT4 count clock, this setting is invalid and input capture does not
occur.
0
1
0
1
0
1
×
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
×
×
TGR3B
is output
compare
register
TGR3B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB3 pin
Capture input
source is channel
4/count clock
IOB0
R/W
4
0
TGR3A I/O Control
0
1
0
1
0
1
IOA3
R/W
3
0
0
1
0
1
0
1
×
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
0 output at compare match
0
1
0
1
0
1
0
1
0
1
×
×
IOA2
R/W
TGR3A
is output
compare
register
TGR3A
is input
capture
register
2
0
*
Rev.7.00 Feb. 14, 2007 page 963 of 1108
IOA1
R/W
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA3 pin
Capture input
source is channel
4/count clock
1
0
×
: Don't care
Appendix B Internal I/O Registers
H'FE82
IOA0
R/W
0
0
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
0 output at compare match
REJ09B0089-0700
× : Don't care
TPU3

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