D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 695

MCU 3V 0K 100-TQFP

D12312SVTE25

Manufacturer Part Number
D12312SVTE25
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12312SVTE25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTE25
HD6412312SVTE25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Notes: 1. Prewriting (setting erase block data to all 0) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 20.3.6, Flash Memory Characteristics.
3. Verify data is read in 16-bit (W) units.
4. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Increment
address
Figure 17.46 Erase/Erase-Verify Flowchart
NG
NG
Set block start address to verify address
H'FF dummy write to verify address
Clear ESU1 (2) bit in FLMCR1 (2)
Clear SWE1 (2) bit in FLMCR1 (2)
Set SWE1 (2) bit in FLMCR1 (2)
Set ESU1 (2) bit in FLMCR1 (2)
Clear EV1 (2) bit in FLMCR1 (2)
Clear E1 (2) bit in FLMCR1(2)
Set EV1 (2) bit in FLMCR1 (2)
Set E1 (2) bit in FLMCR1 (2)
*5
Last address of block?
erasing of all erase
Verify data = all 1?
Set EBR1, EBR2
Read verify data
End of erasing
Disable WDT
Enable WDT
Wait (z) ms
Wait (α) μs
Wait (x) μs
Wait (y) μs
Wait (β) μs
Wait (ε) μs
Wait (η) μs
Wait (θ) μs
Wait (γ) μs
blocks?
End of
n = 1
Start
OK
OK
OK
*1
*2
NG
*2
*4
*2
Start of erase
*2
Halt erase
*2
*2
*2
*2
*3
Rev.7.00 Feb. 14, 2007 page 661 of 1108
Clear SWE1 (2) bit in FLMCR1 (2)
Clear EV1 (2) bit in FLMCR1 (2)
Erase failure
Wait (η) μs
Wait (θ) μs
n ≥ N?
OK
*2
REJ09B0089-0700
NG
*2
Section 17 ROM
n ← n + 1

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