D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 184

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

Section 6 Bus Controller
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
6.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area division unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Rev.7.00 Feb. 14, 2007 page 150 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
Bus Control Register L (BCRL)
Description
Max. 4 words in burst access
Max. 8 words in burst access
Description
External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
External bus release is enabled
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
EAE
R/W
5
1
R/W
—
4
1
R/W
—
3
1
R/W
—
2
1
R/W
—
1
0
(Initial value)
(Initial value)
WAITE
R/W
0
0