D12312SVTE25 Renesas Electronics America, D12312SVTE25 Datasheet - Page 312

• Manufacturer Part Number: D12312SVTE25
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTE25; HD6412312SVTE25

Section 8 I/O Ports
8.10.2
Table 8.17 shows the port E register configuration.
Table 8.17 Port E Registers
Name
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register
Note: * Lower 16 bits of the address.
Port E Data Direction Register (PEDDR)
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 4 to 6 *
• Mode 7 *
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 278 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
Setting PEDDR bits to 1 makes the corresponding port E pins output ports, while clearing the
bits to 0 makes the pins input ports.
Register Configuration
:
:
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
W
7
0
W
6
0
Abbreviation
PEDDR
PEDR
PORTE
PEPCR
W
5
0
W
4
0
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
W
2
0
W
1
0
Address *
H'FEBD
H'FF6D
H'FF5D
H'FF74
W
0
0