DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1035

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

SUBS #1/2/4,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
TAS @ERd *
TRAPA
#x:2
XOR.B #xx8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd R:W 2nd
XOR.L ERs,ERd
XORC #xx:8,CCR
XORC #xx:8,EXR
Reset
excep-
tion
handling
Interrupt
excep-
tion
handling
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
Instruction
Advanced R:W NEXT Internal
Advanced R:W:M
Advanced R:W *
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented
3. Repeated two times to save or restore two registers, three times for three registers, or
4. Start address after return.
5. Start address of the program.
6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery
7. Start address of the interrupt-handling routine.
8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
9. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
8
by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these
bus cycles are not executed.
four times for four registers.
from sleep mode or software standby mode the read operation is replaced by an
internal operation.
R:W NEXT
R:W NEXT
R:W NEXT
R:W 2nd
R:W NEXT
R:W NEXT
R:W 2nd
R:W NEXT
R:W 2nd
R:W NEXT
R:W 2nd
VEC
1
6
R:W NEXT R:B:M EA W:B EA
operation,
1 state
R:W NEXT
R:W 3rd
R:W NEXT
R:W NEXT
R:W
VEC+2
Internal
operation,
1 state
2
W:W
Stack (L)
R:W NEXT
Internal
operation,
1 state
W:W
Stack (L)
3
W:W
Stack (H)
R:W *
W:W
Stack (H)
4
5
W:W
Stack
(EXR)
W:W
Stack
(EXR)
Rev. 4.00 Sep 27, 2006 page 989 of 1130
5
R:W:M
VEC
R:W:M
VEC
6
Appendix A Instruction Set
R:W
VEC+2
R:W
VEC+2
7
REJ09B0327-0400
Internal
operation,
1 state
Internal
operation,
1 state
8
R:W *
R:W *
9
7
7