DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 230

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 7 Data Transfer Controller (DTC)
7.2.2
MRB is an 8-bit register that controls the DTC operating mode.
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer,
multiple data transfers can be performed consecutively in response to a single transfer request.
With data transfer for which CHNE is set to 1, there is no determination of the end of the specified
number of transfers, clearing of the interrupt source flag, or clearing of DTCER.
Bit 7
CHNE
0
1
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
0
1
Bits 5 to 0—Reserved: In the H8S/2148 Group these bits have no effect on DTC operation, and
should always be written with 0.
Rev. 4.00 Sep 27, 2006 page 184 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
DTC Mode Register B (MRB)
Description
End of DTC data transfer (activation waiting state is entered)
DTC chain transfer (new register information is read, then data is transferred)
Description
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
CHNE
Unde-
fined
—
7
DISEL
Unde-
fined
—
6
Unde-
fined
—
—
5
Unde-
fined
—
—
4
Unde-
fined
—
—
3
Unde-
fined
—
—
2
Unde-
fined
—
—
1
Unde-
fined
—
—
0