DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 674

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 20 A/D Converter
20.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
conversion timing. Table 20.4 indicates the A/D conversion time.
As indicated in figure 20.5, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 20.4.
In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
Rev. 4.00 Sep 27, 2006 page 628 of 1130
REJ09B0327-0400
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total conversion
D
φ
Address
Write signal
Input sampling
timing
ADF
Legend:
(1)
(2)
t
t
t
after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D
D
SPL
CONV
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay time
: Input sampling time
: A/D conversion time
Figure 20.5 A/D Conversion Timing
(1)
(2)
t
D
t
SPL
t
CONV
D
and the input sampling time. The

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