DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 237

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 7.2
7.3.2
The DTC operates when activated by an interrupt or by a write to DTVECR by software (software
activation). An interrupt request can be directed to the CPU or DTC, as designated by the
corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding
bit is set to 1, and to the CPU when the bit is cleared to 0.
At the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer)
the interrupt source or the corresponding DTCER bit is cleared. Table 7.3 shows activation
sources and DTCER clearing.
Transfer Mode
Normal mode
Repeat mode
Block transfer mode
One transfer request transfers one
byte or one word
Memory addresses are incremented
or decremented by 1 or 2
Up to 65,536 transfers possible
One transfer request transfers one
byte or one word
Memory addresses are incremented
or decremented by 1 or 2
After the specified number of transfers
(1 to 256), the initial state resumes and
operation continues
One transfer request transfers a block
of the specified size
Block size is from 1 to 256 bytes or
words
Up to 65,536 transfers possible
A block area can be designated at either
the source or destination
Activation Sources
DTC Functions
Activation Source
IRQ
FRT ICI, OCI
8-bit timer CMI
Host interface IBF
SCI TXI or RXI
A/D converter ADI
IIC IICI
Software
Rev. 4.00 Sep 27, 2006 page 191 of 1130
Section 7 Data Transfer Controller (DTC)
Transfer
Source
24 bits
Address Registers
REJ09B0327-0400
Transfer
Destination
24 bits

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