DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 641

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.2.7
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section
25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.
18.3
18.3.1
The HIF (slave mode) is activated by setting the HI12E bit (bit 0) in SYSCR2 to 1 in single-chip
mode. When the HIF (slave mode) is activated, all related I/O ports (data port 3, control ports 8
and 9, and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E
bit and CS4E bit to 1 enables the number of HIF channels to be extended to a four, and makes the
channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated
host interface port.
Table 18.4 shows HIF host interface channel selection and pin operation.
MSTPCRL
Bit 2
MSTP2
0
1
Bit
Initial value
Read/Write
Module Stop Control Register (MSTPCR)
Operation
Host Interface Activation
Description
Host interface module stop mode is cleared
Host interface module stop mode is set
MSTP15
R/W
7
0
MSTP14
R/W
6
0
MSTP13
R/W
5
1
MSTPCRH
MSTP12
R/W
4
1
MSTP11
R/W
3
1
MSTP10
R/W
2
1
MSTP9
R/W
1
1
MSTP8
R/W
0
1
Rev. 4.00 Sep 27, 2006 page 595 of 1130
MSTP7
R/W
7
1
MSTP6
R/W
6
1
MSTP5
R/W
5
1
MSTPCRL
MSTP4
R/W
Section 18 Host Interface
4
1
MSTP3
R/W
3
1
REJ09B0327-0400
MSTP2
R/W
2
1
(Initial value)
MSTP1
R/W
1
1
MSTP0
R/W
0
1

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