DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 274

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 8 I/O Ports
8.3.2
Table 8.6 shows the port 2 register configuration.
Table 8.6
Name
Port 2 data direction register
Port 2 data register
Port 2 MOS pull-up control
register
Note:
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The address output pins maintain their output state in a transition to
software standby mode.
Rev. 4.00 Sep 27, 2006 page 228 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
Mode 1
The corresponding port 2 pins are address outputs, regardless of the P2DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
Modes 2 and 3 (EXPE = 1)
The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set
to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output
ports by setting the IOSE bit to 1.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
* Lower 16 bits of the address.
Register Configuration
Port 2 Registers
P27DDR
W
7
0
P26DDR
W
6
0
Abbreviation
P2DDR
P2DR
P2PCR
P25DDR
W
5
0
P24DDR
W
4
0
R/W
W
R/W
R/W
P23DDR
W
3
0
Initial Value
H'00
H'00
H'00
P22DDR
W
2
0
P21DDR
W
1
0
Address *
H'FFB1
H'FFB3
H'FFAD
P20DDR
W
0
0