DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 649
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
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DF2148ATE20IV
Manufacturer:
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HIRQ Setting/Clearing Contention
If there is contention between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11,
HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held
pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is
executed after completion of the read/write.
18.5
The following points require attention when using the host interface.
(1) Host and slave transmission/reception procedures
(2) Preventing data contention on the HDB
(3) Preventing through-current in pins CS1 to CS4
The host interface provides buffering of asynchronous data from the host and slave processors,
but an interface protocol must be followed to implement necessary functions and avoid data
contention. For example, if the host and slave processors try to access the same input or output
data register simultaneously, the data will be corrupted. Interrupts can be used to design a
simple and effective protocol.
When the HIF function is used (HI12E = 1 in SYSCR2) and channel 3 or channel 4 has been
set as deselected (CS3E = 0 or CS4E = 0 in SYSCR2), apply either of the following usage
conditions.
1. Ensure that the CS pin for the deselected channel is fixed high.
2. Do not perform port B reads.
Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attempting IDR or
ODR access, signal contention will occur within the chip, and a through-current may result.
This usage must therefore be avoided.
Usage Note
Rev. 4.00 Sep 27, 2006 page 603 of 1130
Section 18 Host Interface
REJ09B0327-0400
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