DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 645

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Table 18.7 Fast A20 Gate Output Signal
Notes: 1. Arbitrary data with bit 1 set to 1.
18.3.4
Host interface output can be placed in the high-impedance state according to the state of the
HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register enables the HIFSD pin is slave mode.
The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface
output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the high-impedance state.
At the same time, the host interface input pins (CS1, CS2 or ECS2, CS3, CS4, IOW, IOR, and
HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the
signals of the multiplexed functions of these pins (input block) are similarly fixed internally. As a
result, the host interface I/O pins (HDB7 to HDB0) also go to the high-impedance state.
This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the high-
level state, the pins are restored to their normal operation as host interface pins.
HA0
1
0
1
1
0
1
1
0
1/0
1
0
1/0
1
1
1
1
1
0
1
2. Arbitrary data with bit 1 cleared to 0.
Data/Command
H'D1 command
1 data *
H'FF command
H'D1 command
0 data *
H'FF command
H'D1 command
1 data *
Command other than H'FF
and H'D1
H'D1 command
0 data *
Command other than H'FF
and H'D1
H'D1 command
Command other than H'D1
H'D1 command
H'D1 command
H'D1 command
Any data
H'D1 command
Host Interface Pin Shutdown Function
1
2
1
2
Internal CPU
Interrupt Flag
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
Rev. 4.00 Sep 27, 2006 page 599 of 1130
GA20
(P81)
Q
1
Q (1)
Q
0
Q (0)
Q
1
Q (1)
Q
0
Q (0)
Q
Q
Q
Q
Q
1/0
Q(1/0)
Remarks
Turn-on sequence
Turn-off sequence
Turn-on sequence
(abbreviated form)
Turn-off sequence
(abbreviated form)
Cancelled sequence
Retriggered sequence
Consecutively executed
sequences
Section 18 Host Interface
REJ09B0327-0400