DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 451

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

13.3.9
Using the signals generated/selected with timer connection, it is possible to generate a waveform
based on the composite synchronization signal (blanking waveform).
One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs,
with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the
IVO signal.
The composition logic is shown in figure 13.9.
Mode
Separate
mode
HFBACKI input (positive)
VFBACKI input (positive)
IVO signal (positive)
CBLANK Output
IVI Signal
VSYNCI
input
Figure 13.9 CBLANK Output Waveform Generation
IVO Signal
IVI signal (without fall
modification or IHI
synchronization)
IVI signal (without fall
modification, with IHI
synchronization)
IVI signal (with fall
modification, without IHI
synchronization)
IVI signal (with fall
modification and IHI
synchronization)
IVG signal
Falling edge sensing
Rising edge sensing
Meaning of IVO Signal
VSYNCI input (vertical synchronization signal)
is output directly
Meaningless unless VSYNCI input (vertical
synchronization signal) is synchronized with
HSYNCI input (horizontal synchronization
signal)
VSYNCI input (vertical synchronization signal)
fall is modified before output
VSYNCI input (vertical synchronization signal)
fall is modified and signal is synchronized with
HSYNCI input (horizontal synchronization
signal) before output
Internal synchronization signal is output
Reset
Set
Rev. 4.00 Sep 27, 2006 page 405 of 1130
Q
Section 13 Timer Connection
REJ09B0327-0400
CBLANK signal
(positive)