DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 755

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 23 ROM
(H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
program setting so that the time for one programming operation is within the range of (z1), (z2) or
(z3) µs.
23.7.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least ( ) µs later). The watchdog
timer is cleared after the elapse of ( ) µs or more, and the operating mode is switched to program-
verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of ( ) µs or more. When the flash memory is read in this state (verify data
is read in 16-bit units), the data at the latched address is read. Wait at least ( ) µs after the dummy
write before performing this read operation. Next, the originally written data is compared with the
verify data, and reprogram data is computed (see figure 23.12) and transferred to the reprogram
data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least
( ) µs. If the programming count is less than 6, the 128-byte data in the additional program data
area should be written consecutively to the write addresses, and additional programming
performed. Next clear the SWE bit in FLMCR1, and wait at least ( ) µs. If reprogramming is
necessary, set program mode again, and repeat the program/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times on
the same bits.
Rev. 4.00 Sep 27, 2006 page 709 of 1130
REJ09B0327-0400