DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 608

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 17 Keyboard Buffer Controller
17.1.3
Table 17.1 lists the input/output pins used by the keyboard buffer controller.
Table 17.1 Keyboard Buffer Controller Input/Output Pins
Channel
0
1
2
Note:
17.1.4
Table 17.2 lists the registers of the keyboard buffer controller.
Table 17.2 Keyboard Buffer Controller Registers
Channel
0
1
2
Common
Notes: 1. Lower 16 bits of the address.
Rev. 4.00 Sep 27, 2006 page 562 of 1130
REJ09B0327-0400
* These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK
2. Only 0 can be written in bits 2 and 1, to clear the flags.
Input/Output Pins
Register Configuration
and data I/O pins as KD, omitting the channel designations.
Name
Keyboard control register H
Keyboard control register L
Keyboard data buffer register
Keyboard control register H
Keyboard control register L
Keyboard data buffer register
Keyboard control register H
Keyboard control register L
Keyboard data buffer register
Module stop control register
Name
KBC clock I/O pin (KCLK0)
KBC data I/O pin (KD0)
KBC clock I/O pin (KCLK1)
KBC data I/O pin (KD1)
KBC clock I/O pin (KCLK2)
KBC data I/O pin (KD2)
KBBR0
KBBR1
KBBR2
Abbreviation *
PS2AC
PS2AD
PS2BC
PS2BD
PS2CC
PS2CD
Abbreviation
KBCRH0
KBCRL0
KBCRH1
KBCRL1
KBCRH2
KBCRL2
MSTPCRH
MSTPCRL
R/W
R/(W) *
R/W
R
R/(W) *
R/W
R
R/(W) *
R/W
R
R/W
R/W
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
2
2
Initial Value
H'70
H'70
H'00
H'70
H'70
H'00
H'70
H'70
H'00
H'3F
H'FF
Function
KBC data input/output
KBC data input/output
KBC data input/output
KBC clock input/output
KBC clock input/output
KBC clock input/output
Address *
H'FED8
H'FED9
H'FEDA
H'FEDC
H'FEDD
H'FEDE
H'FEE0
H'FEE1
H'FEE2
H'FF86
H'FF87
1