DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 39

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

18.5 Usage Note........................................................................................................................ 603
Section 19 D/A Converter
19.1 Overview........................................................................................................................... 605
19.2 Register Descriptions ........................................................................................................ 608
19.3 Operation .......................................................................................................................... 611
Section 20 A/D Converter
20.1 Overview........................................................................................................................... 613
20.2 Register Descriptions ........................................................................................................ 616
20.3 Interface to Bus Master ..................................................................................................... 623
20.4 Operation .......................................................................................................................... 624
20.5 Interrupts ........................................................................................................................... 629
20.6 Usage Notes ...................................................................................................................... 630
Section 21 RAM
21.1 Overview........................................................................................................................... 635
21.2 System Control Register (SYSCR) ................................................................................... 636
18.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 601
19.1.1 Features................................................................................................................ 605
19.1.2 Block Diagram ..................................................................................................... 606
19.1.3 Input and Output Pins .......................................................................................... 607
19.1.4 Register Configuration......................................................................................... 607
19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 608
19.2.2 D/A Control Register (DACR) ............................................................................ 608
19.2.3 Module Stop Control Register (MSTPCR) .......................................................... 610
20.1.1 Features................................................................................................................ 613
20.1.2 Block Diagram ..................................................................................................... 614
20.1.3 Pin Configuration................................................................................................. 615
20.1.4 Register Configuration......................................................................................... 616
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 616
20.2.2 A/D Control/Status Register (ADCSR) ............................................................... 617
20.2.3 A/D Control Register (ADCR) ............................................................................ 620
20.2.4 Keyboard Comparator Control Register (KBCOMP) .......................................... 621
20.2.5 Module Stop Control Register (MSTPCR) .......................................................... 622
20.4.1 Single Mode (SCAN = 0) .................................................................................... 624
20.4.2 Scan Mode (SCAN = 1)....................................................................................... 626
20.4.3 Input Sampling and A/D Conversion Time ......................................................... 628
20.4.4 External Trigger Input Timing............................................................................. 629
21.1.1 Block Diagram ..................................................................................................... 635
21.1.2 Register Configuration......................................................................................... 636
.................................................................................................................. 635
................................................................................................. 605
................................................................................................. 613
Rev. 4.00 Sep 27, 2006 page xxxvii of xliv