DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 28

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

2.9
2.10 Usage Note........................................................................................................................ 82
Section 3 MCU Operating Modes
3.1
3.2
3.3
3.4
3.5
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
Rev. 4.00 Sep 27, 2006 page xxvi of xliv
2.8.5
2.8.6
Basic Timing ..................................................................................................................... 78
2.9.1
2.9.2
2.9.3
2.9.4
2.10.1 TAS Instruction.................................................................................................... 82
2.10.2 STM/LDM Instruction ......................................................................................... 82
Overview........................................................................................................................... 83
3.1.1
3.1.2
Register Descriptions ........................................................................................................ 84
3.2.1
3.2.2
3.2.3
3.2.4
Operating Mode Descriptions ........................................................................................... 89
3.3.1
3.3.2
3.3.3
Pin Functions in Each Operating Mode ............................................................................ 90
Memory Map in Each Operating Mode ............................................................................ 91
Overview........................................................................................................................... 103
4.1.1
4.1.2
4.1.3
Reset.................................................................................................................................. 106
4.2.1
4.2.2
4.2.3
Interrupts ........................................................................................................................... 109
Trap Instruction................................................................................................................. 110
Stack Status after Exception Handling.............................................................................. 111
Notes on Use of the Stack ................................................................................................. 112
Bus-Released State............................................................................................... 76
Power-Down State ............................................................................................... 77
Overview.............................................................................................................. 78
On-Chip Memory (ROM, RAM) ......................................................................... 78
On-Chip Supporting Module Access Timing ...................................................... 80
External Address Space Access Timing .............................................................. 81
Operating Mode Selection ................................................................................... 83
Register Configuration......................................................................................... 84
Mode Control Register (MDCR) ......................................................................... 84
System Control Register (SYSCR) ...................................................................... 85
Bus Control Register (BCR) ................................................................................ 87
Serial Timer Control Register (STCR) ................................................................ 88
Mode 1 ................................................................................................................. 89
Mode 2 ................................................................................................................. 89
Mode 3 ................................................................................................................. 90
Exception Handling Types and Priority............................................................... 103
Exception Handling Operation............................................................................. 104
Exception Sources and Vector Table ................................................................... 104
Overview.............................................................................................................. 106
Reset Sequence .................................................................................................... 106
Interrupts after Reset............................................................................................ 108
......................................................................................... 103
.................................................................................. 83