DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 184

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 5 Interrupt Controller
5.5.2
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to
0, and disabled when set to 1. Control level 1 interrupt sources have higher priority.
Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
3. The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address break.
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
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interrupt request is sent to the interrupt controller.
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
bit is set to 1, only NMI and address break interrupt are accepted, and other interrupt requests
are held pending.
current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
handling routine starts at the address indicated by the contents of that vector address.
Interrupt Control Mode 0