DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1079

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SCR1—Serial Control Register 1
SCR2—Serial Control Register 2
SCR0—Serial Control Register 0
Transmit interrupt enable
Receive interrupt enable
Bit
Initial value
Read/Write
0
1
0
1
Transmit-data-empty interrupt
(TXI) request disabled
Transmit-data-empty interrupt
(TXI) request enabled
Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request disabled
Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request enabled
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
Transmit enable
5
0
0
1
Receive enable
0
1
Transmission disabled
Transmission enabled
Multiprocessor interrupt enable
0
1
Reception disabled
Reception enabled
R/W
Multiprocessor interrupts disabled (normal reception mode)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive-error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
Transmit end interrupt enable
RE
0
1
4
0
Clock enable 1 and 0
Transmit-end interrupt (TEI) request disabled
Transmit-end interrupt (TEI) request enabled
0
1
Rev. 4.00 Sep 27, 2006 page 1033 of 1130
0
1
0
1
MPIE
R/W
H'FF8A
H'FFA2
H'FFDA
3
0
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Appendix B Internal I/O Registers
TEIE
R/W
2
0
Internal clock/SCK pin
functions as I/O port
Internal clock/SCK pin
functions as serial clock output
functions as clock output
Internal clock/SCK pin
functions as serial clock output
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
Internal clock/SCK pin
CKE1
R/W
1
0
REJ09B0327-0400
CKE0
R/W
0
0
SCI1
SCI2
SCI0

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