DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 441

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Table 13.5 Examples of TCR and TCSR Settings
Register
TCR in TMR1
TCSR in TMR1
TCR in FRT
TCSR in FRT
Bit(s)
7
6
5
4 and 3 CCLR1, CCLR0
2 to 0
3 to 0
6
1 and 0 CKS1, CKS0
0
Abbreviation
CMIEB
CMIEA
OVIE
CKS2 to CKS0
OS3 to OS0
IEDGB
CCLRA
Contents Description
0
0
0
11
101
0011
1001
0/1
01
0
Rev. 4.00 Sep 27, 2006 page 395 of 1130
Interrupts due to compare-match
and overflow are disabled
TCNT is cleared by the rising edge
of the external reset signal (inverted
IVI signal)
TCNT is incremented on the rising
edge of the external clock (IHI
signal)
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): division by 512
or
when TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: division by
256
0: FRC value is transferred to ICRB
1: FRC value is transferred to ICRB
FRC is incremented on internal
clock: /8
FRC clearing is disabled
on falling edge of input capture
input B (IHI divided signal
waveform)
on rising edge of input capture
input B (IHI divided signal
waveform)
Section 13 Timer Connection
REJ09B0327-0400