DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 563

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Bit 7—I
output buffer as SCL and SDA. This bit is used when implementing the I
only.
Bits 6 and 5—I
CKS0 in ICMR, selects the transfer rate in master mode. For details, see section 16.2.4, I
Mode Register (ICMR).
Bit 4—I
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting module
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details.
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see
section 12.2.4, Timer Control Register (TCR).
Bit 7
IICS
0
1
Bit 4
IICE
0
1
2
2
C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of
C Master Enable (IICE): Controls CPU access to the I
Description
PA7 to PA4 are normal I/O pins
PA7 to PA4 are I/O pins with bus driving capability
Description
CPU access to I
CPU access to I
2
C Transfer Select 1 and 0 (IICX1 and 0): This bit, together with bits CKS2 to
2
2
C bus interface data and control registers is disabled
C bus interface data and control registers is enabled
Rev. 4.00 Sep 27, 2006 page 517 of 1130
Section 16 I
2
C bus interface data and control
2
2
C interface by software
C Bus Interface [Option]
REJ09B0327-0400
(Initial value)
(Initial value)
2
C Bus