DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 38

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

17.2 Register Descriptions ........................................................................................................ 563
17.3 Operation .......................................................................................................................... 568
Section 18 Host Interface
18.1 Overview........................................................................................................................... 583
18.2 Register Descriptions ........................................................................................................ 587
18.3 Operation .......................................................................................................................... 595
18.4 Interrupts ........................................................................................................................... 601
Rev. 4.00 Sep 27, 2006 page xxxvi of xliv
17.1.1 Features................................................................................................................ 559
17.1.2 Block Diagram ..................................................................................................... 561
17.1.3 Input/Output Pins ................................................................................................. 562
17.1.4 Register Configuration......................................................................................... 562
17.2.1 Keyboard Control Register H (KBCRH) ............................................................. 563
17.2.2 Keyboard Control Register L (KBCRL) .............................................................. 565
17.2.3 Keyboard Data Buffer Register (KBBR) ............................................................. 567
17.2.4 Module Stop Control Register (MSTPCR) .......................................................... 567
17.3.1 Receive Operation................................................................................................ 568
17.3.2 Transmit Operation .............................................................................................. 570
17.3.3 Receive Abort ...................................................................................................... 573
17.3.4 KCLKI and KDI Read Timing............................................................................. 576
17.3.5 KCLKO and KDO Write Timing......................................................................... 577
17.3.6 KBF Setting Timing and KCLK Control ............................................................. 578
17.3.7 Receive Timing.................................................................................................... 579
17.3.8 KCLK Fall Interrupt Operation............................................................................ 580
17.3.9 Usage Note........................................................................................................... 581
18.1.1 Features................................................................................................................ 583
18.1.2 Block Diagram ..................................................................................................... 584
18.1.3 Input and Output Pins .......................................................................................... 585
18.1.4 Register Configuration......................................................................................... 586
18.2.1 System Control Register (SYSCR) ...................................................................... 587
18.2.2 System Control Register 2 (SYSCR2) ................................................................. 588
18.2.3 Host Interface Control Register (HICR) .............................................................. 590
18.2.4 Input Data Register 1 (IDR1)............................................................................... 592
18.2.5 Output Data Register 1 (ODR)............................................................................. 592
18.2.6 Status Register (STR) .......................................................................................... 593
18.2.7 Module Stop Control Register (MSTPCR) .......................................................... 595
18.3.1 Host Interface Activation ..................................................................................... 595
18.3.2 Control States....................................................................................................... 597
18.3.3 A20 Gate .............................................................................................................. 597
18.3.4 Host Interface Pin Shutdown Function ................................................................ 599
18.4.1 IBF1, IBF2, IBF3, IBF4....................................................................................... 601
.................................................................................................. 583