DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1060

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Appendix B Internal I/O Registers
DDCSWR—DDC Switch Register
Rev. 4.00 Sep 27, 2006 page 1014 of 1130
REJ09B0327-0400
Notes: 1. Only 0 can be written, to clear the flag.
Bit
Initial value
Read/Write
2. Always read as 1.
DDC mode switch enable
0
1
Automatic switching of IIC channel 0 from formatless mode to I
Automatic switching of IIC channel 0 from formatless mode to I
SWE
R/W
7
0
DDC mode switch
0
1
IIC channel 0 is used with the I
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
R/W
SW
DDC mode switch interrupt enable bit
6
0
0
1
Interrupt when automatic format switching is executed is disabled
Interrupt when automatic format switching is executed is enabled
DDC mode switch interrupt flag
0
1
R/W
IE
No interrupt is requested when automatic format switching
is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
An interrupt is requested when automatic format switching
is executed
[Setting condition]
When a falling edge is detected on the SCL
pin when SWE = 1
5
0
IIC clear bits
CLR3
Bit 3
0
1
R/(W) *
CLR2
Bit 2
—
0
1
IF
4
0
CLR1
2
Bit 1
1
C bus format
—
—
0
1
CLR3
CLR0
Bit 0
W *
3
1
—
—
0
1
0
1
2
H'FEE6
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
CLR2
W *
2
1
2
2
2
C bus format is disabled
C bus format is enabled
Description
CLR1
W *
1
1
2
CLR0
W *
0
1
2
IIC0