DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 909
![IC H8S MCU FLASH 128K 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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26.4.7
(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference
(2) On-chip power supply step-down circuit
values for electrical characteristics shown in this manual. However, actual performance
figures, operating margins, noise margins, and other properties may vary due to differences in
the manufacturing process, on-chip ROM, layout patterns, etc.
When system evaluation testing is carried out using the F-ZTAT version, the same evaluation
tests should also be conducted for the mask ROM version when changing over to that version.
The H8S/2147N F-ZTAT does not incorporate an internal power supply step-down circuit.
When changing over to F-ZTAT versions or mask ROM versions incorporating an internal
step-down circuit, the VCC2 pin has the same pin location as the VCL pin in a step-down
circuit (See figure 26.3).
Therefore, note that the circuit patterns differ between these two types of products.
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
4. Maximum programming time (tP (max))
5. Number of times when the wait time after P-bit setting (z) = 200 µs.
6. Maximum erase time (tE (max))
7. Number of times when the wait time after E-bit setting (z) = 10 ms.
8. Minimum number of times for which all characteristics are guaranteed after rewriting
9. Reference value for 25 C (as a guideline, rewriting should normally function up to this
10. Data retention characteristic when rewriting is performed within the specification range,
Usage Note
The number of writes should be set according to the actual set value of (z) to allow
The number of erases should be set according to the actual set value of (z) to allow
not include the erase verification time.)
tP(max) = wait time after P-bit setting (z)
programming within the maximum programming time (tP(max)).
tE(max) = wait time after E-bit setting (z)
erasing within the maximum erase time (tE(max)).
(Guarantee range is 1 to minimum value).
value).
including the minimum value.
maximum programming count (N)
maximum erase count (N)
Rev. 4.00 Sep 27, 2006 page 863 of 1130
Section 26 Electrical Characteristics
REJ09B0327-0400
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