DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1129

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

TCONRO—Timer Connection Register O
Bit
Initial value
Read/Write
Output enable
0
1
The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/HIRQ1 pin
The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin
HOE
R/W
7
0
Output enable
0
1
The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/KIN1/CIN1 pin
The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin
VOE
R/W
Output enable
6
0
0
1
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the P64/FTIC/KIN4/CIN4 pin
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
CLOE
R/W
Output enable
0
1
5
0
The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin
In mode 1 (expanded mode with on-chip ROM disabled):
In modes 2 and 3 (expanded modes with on-chip ROM enabled):
The P27/A15/PW15/CBLANK pin functions as the A15 pin
The P27/A15/PW15/CBLANK pin functions as the CBLANK pin
Output synchronization signal inversion
0
1
CBOE
R/W
The IHO signal is used directly as the HSYNCO output
The IHO signal is inverted before use as the HSYNCO output
4
0
Rev. 4.00 Sep 27, 2006 page 1083 of 1130
HOINV
R/W
H'FFFD
3
0
Output synchronization signal inversion
0
1
The IVO signal is used directly as
the VSYNCO output
The IVO signal is inverted before
use as the VSYNCO output
Appendix B Internal I/O Registers
VOINV
Output synchronization signal inversion
R/W
0
1
2
0
The CLO signal (CL1, CL2, CL3,
or CL4 signal) is used directly as
the CLAMPO output
The CLO signal (CL1, CL2, CL3,
or CL4 signal) is inverted before
use as the CLAMPO output
Output synchronization
signal inversion
CLOINV
0
1
R/W
The CBLANK signal is
used directly as the
CBLANK output
The CBLANK signal is
inverted before use as
the CBLANK output
1
0
Timer Connection
REJ09B0327-0400
CBOINV
R/W
0
0