DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 483

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SSR is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
Bit 7
TDRE
0
1
Bit 6
RDRF
0
1
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Description
[Clearing conditions]
[Setting conditions]
[Clearing conditions]
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Description
When 0 is written in TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR
When 0 is written in RDRF after reading RDRF = 1
When the DTC is activated by an RXI interrupt and reads data from RDR
Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 437 of 1130
REJ09B0327-0400
(Initial value)
(Initial value)

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