DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 290

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 I/O Ports
Port 5 Data Direction Register (P5DDR)
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are
reserved.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR,
P5DDR, and P5DR specifications.
Port 5 Data Register (P5DR)
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50).
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly,
regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0,
the pin states are read.
Bits 7 to 3 are reserved; they cannot be modified and are always read as 1.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 244 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
7
1
7
1
6
1
6
1
5
1
5
1
4
1
4
1
3
1
3
1
P52DDR
P52DR
R/W
W
2
0
2
0
P51DDR
P51DR
R/W
W
1
0
1
0
P50DDR
P50DR
R/W
W
0
0
0
0

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