DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 683

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

21.3
21.3.1
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to
H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the off-chip address space.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
21.3.2
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed.
Undefined values are read from these bits, and writing is invalid.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Operation
Expanded Mode (Modes 1, 2, 3 (EXPE = 1))
Single-Chip Mode (Modes 2 and 3 (EXPE = 0))
Rev. 4.00 Sep 27, 2006 page 637 of 1130
REJ09B0327-0400
Section 21 RAM