DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 481
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
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Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR
set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Note:
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted.
Note:
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
Bit 3
MPIE
0
1
Bit 2
TEIE
0
1
* When receive data including MPB = 0 is received, receive data transfer from RSR to
* TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR,
is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is
set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Description
Multiprocessor interrupts disabled (normal reception performed)
[Clearing conditions]
Multiprocessor interrupts enabled *
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Description
Transmit-end interrupt (TEI) request disabled *
Transmit-end interrupt (TEI) request enabled *
When the MPIE bit is cleared to 0
When data with MPB = 1 is received
Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Sep 27, 2006 page 435 of 1130
REJ09B0327-0400
(Initial value)
(Initial value)
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