DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 17

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Item
23.6.1 Boot Mode
23.7.2 Program-Verify
Mode
Figure 23.12
Program/Program-Verify
Flowcharts
23.10.4 Memory Read
Mode
Figure 23.17 Timing
Waveforms when
Entering Another Mode
from Memory Read
Mode
Page
705
710
721
Revision (See Manual for Details)
Description amended
H'(FF)E088 and above
Note *6 added to figure 23.12
Note: Use a (z3) s write pulse for additional
Figure 23.17 amended
FA17 to FA0
Note 7: Write Pulse Width
Number of Writes n
FO7 to FO0
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
programming.
Clear PSU bit in FLMCR2
1000
998
999
Set PSU bit in FLMCR1
Sub-routine write pulse
10
11
12
13
Clear P bit in FLMCR1
storage area (128 kbytes)
1
2
3
4
5
6
7
8
9
. .
.
Reprogram data storage
Additional program data
Set P bit in FLMCR1
Program data storage
Enable WDT
Disable WDT
area (128 bytes)
area (128 bytes)
Wait (y) s
Wait ( ) s
Wait ( ) s
WE
End sub
OE
CE
RAM
Write Time (z *
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
. .
.
6
) sec
Increment address
*6
*5
*6
*6
Memory read mode
Write 128-byte data in additional program data
Transfer reprogram data to reprogram data area *4
Store 128-byte program data in program
area in RAM consecutively to flash memory
NG
Write 128-byte data in RAM reprogram data
data area and reprogram data area
Additional program data computation
Rev. 4.00 Sep 27, 2006 page xv of xliv
H'FF dummy write to verify address
Address stable
Transfer additional program data
area consecutively to flash memory
to additional program data area
Reprogram data computation
Additional write pulse (z3) s
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
(z1) s or (z2) s
Read verify data
data verification?
End of 128-byte
Program data =
Wait (x) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Write pulse
Wait ( ) s
verify data?
OK
OK
OK
m = 0?
m = 0
6
n = 1
6
Start
n?
OK
n?
OK
Data
Sub-routine-call
NG
NG
NG
NG
*6
t
*6
*4
*1
See Note 7 for pulse width
*6
*6
*6
*2
*4
*3
*6
*1
*6
nxtc
m = 1
Other mode command write
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
t
Clear SWE bit in FLMCR1
ces
t
f
Programming failure
Wait ( ) s
n
t
wep
1000?
t
OK
H'XX
ds
t
dh
t
r
t
ceh
NG
n
n + 1
*6