DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 1122

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Appendix B Internal I/O Registers
TCSRY—Timer Control/Status Register Y
Rev. 4.00 Sep 27, 2006 page 1076 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
TCSRY
Note:
* Only 0 can be written in bits 7 to 5, to clear the flags.
Compare match flag B
R/(W) *
CMFB
0
1
7
0
[Clearing conditions]
• When 0 is written in CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt
[Setting condition]
When TCNT = TCORB
R/(W) *
Compare match flag A
CMFA
0
1
6
0
[Clearing conditions]
• When 0 is written in CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt
[Setting condition]
When TCNT = TCORA
R/(W) *
Timer overflow flag
OVF
0
1
5
0
[Clearing condition]
When 0 is written in OVF after reading OVF = 1
[Setting condition]
When TCNT overflows from H'FF to H'00
Input capture interrupt enable
0
1
ICIE
R/W
4
0
Interrupt request by ICF (ICIX) is disabled
Interrupt request by ICF (ICIX) is enabled
Output select 3 and 2
0
1
Output select 1 and 0
OS3
R/W
H'FFF1
0
1
0
1
0
1
3
0
No change at compare match B
0 output at compare match B
1 output at compare match B
Output inverted at compare
match B (toggle output)
0
1
0
1
OS2
R/W
No change at compare match A
0 output at compare match A
1 output at compare match A
Output inverted at compare
match A (toggle output)
2
0
OS1
R/W
1
0
OS0
R/W
0
0
TMRY

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