DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 134

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 3 MCU Operating Modes
3.2.4
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions),
and also selects the TCNT input clock. For details of functions other than register access control,
see the descriptions of the relevant modules. If a module controlled by STCR is not used, do not
write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—I
port A and the operation of the I
details, see section 16.2.7, Serial/Timer Control Register (STCR).
Bit 4—I
and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and
control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),
and the SCI control registers (SMR, BRR, and SCMR).
Bit 4
IICE
0
1
Rev. 4.00 Sep 27, 2006 page 88 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
2
C Master Enable (IICE): Controls CPU access to the I
Serial Timer Control Register (STCR)
Description
Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used
for SCI1 control register access
Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used
for SCI2 control register access
Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used
for SCI0 control register access
Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used
for IIC1 data register and control register access
Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used
for PWMX data register and control register access
Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used
for IIC0 data register and control register access
2
C Control (IICS, IICX1, IICX0): These bits control the bus buffer function of the
IICS
R/W
7
0
IICX1
R/W
6
0
2
C bus interface when the on-chip IIC option is included. For
IICX0
R/W
5
0
IICE
R/W
4
0
FLSHE
R/W
3
0
2
C bus interface data registers
R/W
—
2
0
ICKS1
R/W
1
0
(Initial value)
ICKS0
R/W
0
0