DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 789

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 25 Power-Down State
Section 25 Power-Down State
25.1
Overview
In addition to the normal program execution state, this LSI have a power-down state in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip supporting modules, and
so on.
This LSI has the following operating modes:
1. High-speed mode
2. Medium-speed mode
3. Subactive mode
4. Sleep mode
5. Subsleep mode
6. Watch mode
7. Module stop mode
8. Software standby mode
9. Hardware standby mode
Of these, 2 to 9 are power-down modes. Sleep mode and subsleep mode are CPU modes, medium-
speed mode is a CPU and bus master mode, subactive mode is a CPU, bus master, and on-chip
supporting module mode, and module stop mode is an on-chip supporting module mode
(including bus masters other than the CPU). Certain combinations of these modes can be set.
After a reset, the MCU is in high-speed mode and module stop mode (excluding the DTC).
Table 25.1 shows the internal chip states in each mode, and table 25.2 shows the conditions for
transition to the various modes. Figure 25.1 shows a mode transition diagram.
Rev. 4.00 Sep 27, 2006 page 743 of 1130
REJ09B0327-0400

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