DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 223

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

6.7
6.7.1
This LSI have a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and the DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.7.2
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
both bus masters, the bus request acknowledge signal is sent to the one with the higher priority.
When a bus master receives the bus request acknowledge signal, it takes possession of the bus
until that signal is canceled.
The order of priority of the bus masters is as follows:
(High)
Bus Arbitration
Overview
Operation
DTC
>
CPU
(Low)
Rev. 4.00 Sep 27, 2006 page 177 of 1130
Section 6 Bus Controller
REJ09B0327-0400