DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 810
![IC H8S MCU FLASH 128K 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 25 Power-Down State
25.11
25.11.1 Overview of Direct Transition
There are three operating modes in which the CPU executes programs: high-speed mode, medium-
speed mode, and subactive mode. A transition between high-speed mode and subactive mode
without halting the program is called a direct transition. A direct transition can be carried out by
setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition,
direct transition interrupt exception handling is started.
Direct Transition from High-Speed Mode to Subactive Mode: If a SLEEP instruction is
executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in
LPWRCR, and the PSS bit in TSCR (WDT1) are all set to 1, a transition is made to subactive
mode.
Direct Transition from Subactive Mode to High-Speed Mode: If a SLEEP instruction is
executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0
and the DTON bit is set to 1 in LPWRCR, and the PSS bit in TSCR (WDT1) is set to 1, after the
elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to high-
speed mode.
25.12
1. When making a transition to subactive mode or watch mode, set the DTC to enter module stop
2. The on-chip peripheral modules (DTC and TPU) which halt operation in subactive mode
Rev. 4.00 Sep 27, 2006 page 764 of 1130
REJ09B0327-0400
mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that
they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant
bits in MSTPCR) until a transition from subactive mode to high-speed mode or medium-speed
mode has been performed.
If a DTC activation source occurs in sub-active mode, the DTC will be activated only after
module stop mode has been cleared and high-speed mode or medium-speed mode has been
entered.
cannot clear an interrupt in subactive mode. Therefore, if a transition is made to sub-active
mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the
interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter
subactive mode or watch mode.
Direct Transition
Usage Notes
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