DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 702

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 22 ROM
22.6.1
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after this group MCU’s pins have been set to boot mode, the boot
program built into the MCU is started and the programming control program prepared in the host
is serially transmitted to the MCU via the SCI. In the MCU, the programming control program
received via the SCI is written into the programming control program area in on-chip RAM. After
the transfer is completed, control branches to the start address of the programming control
program area and the programming control program execution state is entered (flash memory
programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 22.7, and the boot program mode
execution procedure in figure 22.8.
Rev. 4.00 Sep 27, 2006 page 656 of 1130
REJ09B0327-0400
Boot Mode
Host
(Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Figure 22.7 System Configuration in Boot Mode
Verify data transmission
Write data reception
RxD1
TxD1
SCI1
This group chip
Flash memory
On-chip RAM

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