DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 632

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 18 Host Interface
18.1.4
Table 18.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,
ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 18.2 Host Interface Registers
Name
System control register
System control register 2 SYSCR2
Host interface control
register 1
Host interface control
register 2
Input data register 1
Output data register 1
Status register 1
Input data register 2
Output data register 2
Status register 2
Input data register 3
Output data register 3
Status register 3
Input data register 4
Output data register 4
Status register 4
Module stop control
register
Notes: 1. Bits 5 and 3 are read-only bits.
Rev. 4.00 Sep 27, 2006 page 586 of 1130
REJ09B0327-0400
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
3. Address when accessed from the slave processor. The lower 16 bits of the address are
4. Pin inputs used in access from the host processor.
5. The HA0 input discriminates between writing of commands and data.
Register Configuration
processor.
shown.
Abbrevia-
tion
SYSCR
HICR
HICR2
IDR1
ODR1
STR1
IDR2
ODR2
STR2
IDR3
ODR3
STR3
IDR4
ODR4
STR4
MSTPCRH R/W
MSTPCRL
Slave
R/W *
R/W
R/W
R/W
R/(W) *
R/W
R/(W) *
R
R/W
R/(W) *
R
R/W
R/(W) *
R/W
R
R/W
R
1
R/W
2
2
2
2
Host
—
—
R
R
R
W
R
R
W
R
R
—
—
—
—
W
R
W
Initial
Value
H'09
H'00
H'F8
H'F8
—
—
H'00
—
—
H'00
—
—
H'00
—
—
H'00
H'3F
H'FF
Slave
Address *
H'FFC4
H'FF83
H'FFF0
H'FE80
H'FFF4
H'FFF5
H'FFF6
H'FFFC
H'FFFD
H'FFFE
H'FE84
H'FE85
H'FE86
H'FE8C
H'FE8D
H'FE8E
H'FF86
H'FF87
3
CS1
CS1
—
—
—
—
0
0
0
1
1
1
1
1
1
1
1
1
—
—
CS1
CS1
CS2
CS2
—
—
—
—
1
1
1
0
0
0
1
1
1
1
1
1
—
—
CS2
CS2
Master Address *
CS3
CS3
CS3
CS3
—
—
—
—
1
1
1
1
1
1
0
0
0
1
1
1
—
—
CS4
CS4
CS4
CS4 HA0
—
—
—
—
1
1
1
1
1
1
1
1
1
0
0
0
—
—
4
—
—
—
—
0/1 *
0
1
0/1 *
0
1
0/1 *
0
1
0/1 *
0
1
—
—
5
5
5
5