DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 778

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 24 Clock Pulse Generator
24.1.2
The clock pulse generator is controlled by the standby control register (SBYCR) and low-power
control register (LPWRCR). Table 24.1 shows the register configuration.
Table 24.1 CPG Registers
Name
Standby control register
Low-power control register
Note:
24.2
24.2.1
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 to 2 are described here. For a description of the other bits, see section 25.2.1, Standby
Control Register (SBYCR).
SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock
for high-speed mode and medium-speed mode.
When operating the device after a transition to subactive mode or watch mode bits SCK2 to SCK0
should all be cleared to 0.
Rev. 4.00 Sep 27, 2006 page 732 of 1130
REJ09B0327-0400
Bit
Initial value
Read/Write
* Lower 16 bits of the address.
Register Configuration
Register Descriptions
Standby Control Register (SBYCR)
SSBY
R/W
7
0
STS2
R/W
6
0
Abbreviation
SBYCR
LPWRCR
STS1
R/W
5
0
R/W
R/W
R/W
STS0
R/W
4
0
—
—
3
0
Initial Value
H'00
H'00
SCK2
R/W
2
0
SCK1
R/W
1
0
Address *
H'FF84
H'FF85
SCK0
R/W
0
0