DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 590
DF2148ATE20
Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148ATE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20
HD64F2148ATE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
Table 16.7 Permissible SCL Rise Time (t
IICX
0
1
Rev. 4.00 Sep 27, 2006 page 544 of 1130
REJ09B0327-0400
The I
and 300 ns. The I
table 16.6. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
BUFO
SCLLO
t
Indication
7.5t
17.5t
cyc
fails to meet the I
in high-speed mode and t
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
cyc
2
C Bus Interface [Option]
Standard
mode
High-speed
mode
Standard
mode
High-speed
mode
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
I
Specification
(Max.)
1000 ns
300 ns
1000 ns
300 ns
STASO
2
C Bus
in standard mode fail to satisfy the I
Sr
) Values
Sr
/t
5 MHz
1000 ns 937 ns
300 ns
1000 ns 1000 ns
300 ns
Time Indication
Sf
=
. Possible solutions that should be investigated
8 MHz
300 ns
300 ns
=
2
C bus interface specifications may
10 MHz
750 ns
300 ns
1000 ns 1000 ns 875 ns
300 ns
2
=
C bus.
2
C bus interface
2
C bus.
16 MHz
468 ns
300 ns
300 ns
=
cyc
, as shown in
20 MHz
375 ns
300 ns
300 ns
=
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