DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 341

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

10.2.2
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The CPU can read
and write the PWM (D/A) data register values, but since DADRA and DADRB are 16-bit
registers, data transfers between them and the CPU are performed using a temporary register
(TEMP). See section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an
analog value is set in the upper 14 bits of the PWM (D/A) data register.
In each base cycle, the DACNT value is continually compared with these upper 14 bits to
determine the duty cycle of the output waveform, and to decide whether to output a fine-
adjustment pulse equal in width to the resolution. To enable this operation, the data register must
be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is
outside this range, the PWM output is held constant.
A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and
DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data
bits correspond to the two highest counter (DACNT) bits.
Bit (CPU)
Bit (Data)
DADRA
Initial value
Read/Write
DADRB
Initial value
Read/Write
D/A Data Registers A and B (DADRA and DADRB)
DA13
DA13
R/W
R/W
15
13
1
1
DA12
DA12
R/W
R/W
14
12
1
1
DA11
DA11
R/W
R/W
13
11
1
1
DA10
DA10
R/W
R/W
DADRH
12
10
1
1
DA9
R/W
DA9
R/W
11
9
1
1
DA8
R/W
DA8
R/W
10
8
1
1
DA7
R/W
DA7
R/W
9
7
1
1
DA6
R/W
DA6
R/W
8
6
1
1
Rev. 4.00 Sep 27, 2006 page 295 of 1130
DA5
R/W
DA5
R/W
7
5
1
1
Section 10 14-Bit PWM Timer (PWMX)
DA4
R/W
DA4
R/W
6
4
1
1
DA3
R/W
DA3
R/W
5
3
1
1
DADRL
DA2
R/W
DA2
R/W
4
2
1
1
DA1
R/W
DA1
R/W
3
1
1
1
REJ09B0327-0400
DA0
R/W
DA0
R/W
2
0
1
1
CFS
R/W
CFS
R/W
—
1
1
1
REGS
R/W
—
—
—
0
1
1