R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1022

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20. Graphics Data Translation Accelerator (GDTA)
20.3.12 CL Command FIFO (CLCF)
CLCF is in the CL register block and receives commands. This register uses the FIFO method and
recognizes four command parameters according to the writing order. This register does not retain
the written values. This register is always read as 0.
Notes: 1. Setting Method
Rev.1.00 Jan. 10, 2008 Page 990 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 0
R/W:
R/W:
BIt:
BIt:
•
•
•
•
Bit Name
CL_CF
Input Y pointer: Pointer for input Y data (Input Y data storing address)
Input U pointer: Pointer for input U data (Input U data storing address)
Input V pointer: Pointer for input V data (Input V data storing address)
Output pointer: Pointer for output data (Output data storing address)
When accessing this register, the CL_EN bit in GACER should be set to 1. Access is
possible only when the CL_EN bit is set to 1. If the CL_EN bit is 0, access is invalid
(writing is invalid; the result of reading is indefinite).
The following shows the parameter contents assumed according to the writing order:
Writing Order
CL command parameter 1
CL command parameter 2
CL command parameter 3
CL command parameter 4
31
15
W
W
0
0
30
14
W
W
0
0
29
13
W
W
0
0
Initial
Value
0
28
12
W
W
0
0
R/W
W
27
11
W
W
0
0
26
10
W
W
0
0
Description
Command FIFO register
Setting Contents
Input Y pointer
Input U pointer
Input V pointer
Output pointer
25
W
W
0
9
0
24
W
W
0
8
0
CL_CF
CL_CF
23
W
W
0
7
0
22
W
W
0
6
0
21
W
W
0
5
0
20
W
W
0
4
0
CL command
19
W
W
0
3
0
18
W
W
0
2
0
17
W
W
0
1
0
16
W
W
0
0
0