R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 569
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 569 of 1694
- Download datasheet (9Mb)
command, the constraint tRCD between the ACT command and READ command, and the
constraint tRAS between the ACT command and the PRE command are involved. The DBSC2
waits to issue commands until each of the constraints is satisfied.
MCK0,
MCK1
MCKE
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
MA[10]
MBA[2:0]
MDQS[3:0]
MDM[3:0]
MDQ[31:0]
SDRAM
command
bank A
PRE
Valid
Invalid
tRP
= 3 cycles
Invalid
Invalid
Figure 12.14 tRP, tRCD, CL, and tRAS
High level
bank A
ACT
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
tRAS
= 9 cycles
= 3 cycles
tRCD
READ
bank A
Invalid
Valid
Valid
Valid
CL
= 3 cycles
Rev.1.00 Jan. 10, 2008 Page 537 of 1658
12. DDR2-SDRAM Interface (DBSC2)
Invalid
Invalid
Read data
Invalid
bank A
REJ09B0261-0100
PRE
Valid
Invalid
Invalid
Invalid
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